The semiconductor technology has been following Moore's' law relentlessly over the past two decades, with device densities now containing several million transistors. This has translated into ever increasing challenges in testing and packaging of these devices due to greatly increased need for input/output (I/O) terminal pads and decreased pad size and spacing. The leading-edge pad pitches and sizes are under 50 μm, a limiting value for wirebond technology. This has hastened the migration to area array solder bump, or flip chip bonding, which accommodates increased number I/O pads, significantly relaxing the pad size and density constraints for many memory devices. For ASICs and microprocessor type devices, number of area array I/Os numbers, have routinely exceeded a thousand pads on a single device or chip, requiring ever smaller pad sizes and pitches, currently reaching 75 μm pads on 150 μm, respectively. The area array technology brings its own unique challenges in processing, package reliability, and testing. Added to these are the challenges to reduce the costs in device fabrication, testing, and packaging.
These challenges have been met though technological innovations in testing and packaging, materials, and structures. For packaging, the industry has developed low cost flip chip bonding substrates shown in FIG. 1.
Flip chip solder interconnection, also called Controlled Collapse Chip Connection or C4, for short, was first introduced by IBM more than 30 years ago. Kumar et. al. (U.S. Pat. No. 4,301,324) developed ceramic substrates of nearly same coefficient of thermal expansion, (CTE), as the device chip, allowing for very highly reliable solder connections. Today's lower cost flip chip packages are made from plastic packages with high Coefficient of Thermal Expansion (CTE). In recent years the rest of the industry has also widely adopted this method of interconnection for connecting the chip directly to the board, inviting serious reliability problems involving fatigue failures in the solder joints. Adoption of flip chip, area array terminals for even low I/O devices has enabled packaging these devices on the wafer itself, thorough the so called Wafer Level Packaging, (WLP), methods, greatly reducing cost.
Reliability of flip chip solder joints to second level packages such as printed wiring boards, (PWB), is a serious concern, and becoming more so as the pad sizes decrease. One widely adopted mitigation strategy to enhance solder joint reliability is to use a polymer fill under the chip (so called ‘underfill), entailing extra costs for process, materials, equipment, and yield loss. Another strategy, just coming into use, particularly for microprocessor device chips, is the so-called ‘copper bumps’, once again adding cost and complexity. This concern seriously jeopardizes the migration to smaller pad sizes pitches projected by the industry. While they add much cost and process complexity, these measures only improve fatigue life by less than a third.
Industry has also developed a versatile vertical probe technology using discrete metal wires, so-called COBRA probes, to test these area array chips. The increased numbers, densities, decreased sizes of area-array pads on device chip have brought about a commensurate need for new vertical probe technologies. Available vertical probe technologies are complex, expensive, and delicate. The introduction of micro-fabricated cantilever probes has met the challenges in testing the closely spaced, smaller wirebond pads. The so-called multi-DUT probes constructed from these have enabled greatly increased productivity though their ability to contact many dies simultaneously i.e. increased ‘test parallelism’.
One common method to form arrays of vertical probes is to attach metal wire extensions to the co-planar pads on the surface of substrates, same ones used for packaging the dies. The wire extensions are essentially truncated gold wire bonds formed on the gold plated substrate pads. The package provides the necessary electrical connections to the ‘wire probes’, routing them to conveniently spaced and located interconnection terminal pads used to join to the next level of interconnection, such as a printed wiring board, (PWB). This routing can be either to pads located on the same side of the central probe array, i.e. co-planar routing or, as is more common, to the opposite surface of the surface of the package. In this context, the package is often referred to as the ‘space transformer’ because, invariably, the pad spacing of the terminal pads are much wider than that of the probe array. In this document the terms substrates and space transformers are used interchangeably. The space transformers are generally made of ceramic packages, often multi-layer ceramic packages with several levels of internal wiring, terminating on both the probe side and the ‘board side’, in co-planar pads that may be plated with nickel and gold. To form the probe array, soft gold wires are ultrasonically bonded to the pads, and specially shaped before truncating and planarizing the tops. The soft gold wires may be stiffened by coating with polymer, or with nickel alloys. Special tips and ‘electro-formed’ arrays of cantilever beams of a suitable metal alloy are attached to the ends of the probes from wafer templates. Yet another method for forming probes involves building probe arrays on space transformers by lithographically patterned and plated thin films. Here, multiple plating steps are needed to obtain probe structures sufficiently tall, often as much as 0.5 -to 2 mm, to overcome the global and local positional variations in the locations of the test pads on the wafers. Such micro-fabrication methods, can be carried out either right on the space transformer, or fabricated separately and transferred to the space transformer. The wire-bond probes and the micro fabricated probes are both delicate structures, which when bent or broken, are hard to repair or replace. Invariably, the probe cross-sections in these structures are significantly smaller than the diameters of the pads on the space transformer to which they are joined. Also they are adhered to the pads of the space transformer over-plating a hard metal on the base or joined with solder or braze. For these reasons, multi-Device Under Test (DUT) probes are fragile and, expensive.
In the prior art wafer probe structures discussed above, the process complexities, and the high fabrication costs, are the direct result of the need to elevate the probe tips significantly above the surface of the space transformer. This, in turn, is dictated by the requirement for the probe tips to bend and conform to the thousands of test pads on a wafer, compensating for the expected variations in probe heights, i.e. planarity, and variations in the wafer thickness, in pad sizes, locations, together adding up to 100-500 microns. Depending on the size of the probe array, the probe heights required to compensate for these factors can range from 25 μm, for a single DUT, area-array probe, to 500 μm for a multi-DUT probe. Some bending or compliance of the probe is also required to provide a level of ‘scrub’ needed to break though oxide formed on the wafer terminals. Sophisticated probe array positioning and tilting schemes can decrease these heights, somewhat.